1. Field of the Invention
The present invention relates generally to a precharge type multiplexer with complementary signal input pairs and a complementary signal output pair, more particularly, to a column switch circuit as the multiplexer for use in a memory circuit.
2. Description of the Related Art
FIG. 7 is a schematic circuit diagram of a prior art multiplexer 10. In FIG. 7, an asterisk * added on the head of reference characters of a signal or signal line denotes active low.
The multiplexer 10 is used, for example, as a column select circuit in a memory circuit. In FIG. 7, for simplification, a case is shown in which the multiplexer 10 has a data signal input of 4 bits.
Input signal lines SI1 to SI4 are connected through respective switches 11 to 14 to a data bus line DB, and input data signal lines *SI1 to *SI4 complementary to the input data signal lines SI1 to SI4 are connected through respective switches 15 to 18 to data bus line *DB complementary to the data bus line DB. Each of the switches 11 to 18 is configured such that a PMOS transistor and an NMOS transistor are connected in-parallel to each other. To the gates of the NMOS transistors of the switches 11 to 14, there are connected respective input selection lines C1 to C4 to which outputs of a decoder 20 are provided, while to the gates of the PMOS transistors of the switches 11 to 14, there are connected respective input selection lines *C1 to *C4 complementary to the input selection lines C1 to C4. The decoder 20 turns on a selected pair of switches according to a selection control signal SEL of 2 bits when an output enable signal EN is active.
The data bus lines DB and *DB are connected to the outputs of a charge circuit 21 receiving a precharge signal *PCG which is driven low prior to selection control so that the data bus lines DB and *DB are precharged to the same potential as a logic high of the input data signal. A potential difference between the data bus lines DB and *DB is provided to a sense amplifier circuit 22 to amplify the difference and output as complimentary output signals SO and *SO.
FIG. 8 is a waveform diagram showing operation in a case where the input data signal lines SI1 and *SI1 of FIG. 7 are selected and signals SO and *SO are outputted.
At first, the output enable signal EN is inactive and all of the switches 11 to 18 are off. In this state, the precharge signal *PCG is driven low and the data bus lines DB and *DB are precharged high by the charge circuit 21. In the period of this operation, the input data signals of 4 bits are provided to the multiplexer 10. As shown in FIG. 7, it is assumed that the input data signal lines SI1 and *SI2 to *SI4 are high (xe2x80x98Hxe2x80x99), while the input data signal lines *SI1 and SI2 to SI4 are low (xe2x80x98Lxe2x80x99).
Then, the precharge signal *PCG is driven high to cease the precharge and cause both of the data bus lines DB and *DB to enter into a floating state. On the other hand, the output enable signal EN becomes active and the input selection lines C1 and *C1 are driven high and low, respectively, by the decoder 20 to turn on the switches 11 and 15. Since the input data signal line *SI1 is low, a positive charge moves from the data bus line *DB through the switch 11 to the input data signal line SI1 to lower the potential of the data bus line *DB. In a case of a memory circuit, since resistance and parasitic capacitance of the input data signal lines SI1 to SI4 and *SI1 to *SI4 and the on-resistance of the switches 11 and 18 are comparatively large, a time constant, which is a product of resistance and capacitance, is also comparatively large, thereby the lowering of the potential is gradual.
A sense amplifier drive signal SAD is driven high to activate the sense amplifier circuit 22, and thereby a potential difference between the data bus lines DB and *DB is amplified in the sense amplifier circuit 22 to output as signals SO and *SO. In order to prevent a malfunction of the sense amplifier circuit 22 by noise, the sense amplifier circuit 22 is activated at a time when it is estimated that the potential difference xcex94V between the data bus lines DB and *DB has become about 100 mV.
It is possible to speed up the operating speed of a circuit if threshold voltages of all the transistors thereof are lowered.
However, the threshold voltages of the switching transistors 11 to 18 also lowered; therefore leakage current through the switches in an off state increases, and transfer of a positive charge from the data bus line DB of xe2x80x98Hxe2x80x99 through the switches 12 to 14 to the input data signal lines SI2 to SI4 of xe2x80x98Lxe2x80x99 increases with the result that decrease occurs in the potentials of not only the data bus line *DB but also the data bus line DB. Hence, a time interval from the activation of the output of the decoder 20 to the time point when the potential xcex94V reaches about 100 mV becomes longer, and therefore a necessity arise for delaying the start point of activation of the sense amplifier circuit 22, thereby hindering realization of a high-speed operation.
Although there arises variations in potential difference between the data bus lines DB and *DB since the leakage current differs according to the input data of the multiplexer 10, at a design phase, it is required to avoid the malfunction even in the worst condition conceivable; therefore the variations retard higher speed operation.
Accordingly, it is an object of the present invention to provide a multiplexer capable of reducing variations in potential difference between a pair of complementary data bus lines caused by leakage current flowing through switches in an off state to increase an operating speed.
In one aspect of the present invention, there is provided a multiplexer circuit comprising: a plurality of switch circuits connected to first and second output bus lines to be precharged to the same potential; and a selection control circuit selectively turning on one of the plurality of switch circuits.
Each of the plurality of switch circuits includes: first and second switches, connected between a first input signal line and the first output bus line and between a second input signal line which is complementary to the first input signal line and the second output bus line, respectively, turned on/off by the selection control circuit; and first and second dummy switches, connected between the first input signal line and the second output bus line and between the second input signal line and the first output bus line, respectively, normally tuned off.
With this configuration, if the first and second switches of each switch circuit are off, complementary signals are provided onto the first and second input signal lines of each switch circuit, and the first and second output bus lines are precharged to the same potential, a leakage current flowing between the first output bus line and input signal lines connected to the first output bus line through switches including dummy switches will become almost equal to a leakage current flowing between the second output bus line and input signal lines connected to the second output bus line through switches including dummy switches. Hence, the potential difference between the first and second data bus lines will keep to be almost zero, which is substantially the same as a case of no leakage current to a sense amplifier circuit amplifying this potential difference.
Therefore, when one of the switch circuits is selected by the selection control circuit, almost no influence of leakage current is exerted on the potential difference between the first and second data bus lines. Thereby variations in the potential difference caused by input signal values provided to the multiplexer are prevented, and reduction in the potential difference caused by leakage current is suppressed, resulting in realizing a high speed operation.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.